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The development of micro- and nanotechnology for biomedical applications has defined the cutting edge of medical technology for over three decades, as advancements in fabrication technology developed originally in the semiconductor industry have been applied to solving ever-more complex problems in medicine and biology. These technologies are ideally suited to interfacing with life sciences, since they are on the scale lengths as cells (microns) and biomacromolecules (nanometers). In this paper, we review the state of the art in bionanotechnology and bioMEMS (collectively BNM), including developments and challenges in the areas of BNM, such as microfluidic organ-on-chip devices, oral drug delivery, emerging technologies for managing infectious diseases, 3D printed microfluidic devices, AC electrokinetics, flexible MEMS devices, implantable microdevices, paper-based microfluidic platforms for cellular analysis, and wearable sensors for point-of-care testing.

Two dimensional (2D) semiconductors have been established as promising candidates to break through the short channel effect that existed in Si metal-oxide-semiconductor field-effect-transistor (MOSFET), owing to their unique atomically layered structure and dangling-bond-free surface. The last decade has witnessed the significant progress in the size scaling of 2D transistors by various approaches, in which the physical gate length of the transistors has shrank from micrometer to sub-one nanometer with superior performance, illustrating their potential as a replacement technology for Si MOSFETs. Here, we review state-of-the-art techniques to achieve ultra-scaled 2D transistors with novel configurations through the scaling of channel, gate, and contact length. We provide comprehensive views of the merits and drawbacks of the ultra-scaled 2D transistors by summarizing the relevant fabrication processes with the corresponding critical parameters achieved. Finally, we identify the key opportunities and challenges for integrating ultra-scaled 2D transistors in the next-generation heterogeneous circuitry.

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

The increasing vulnerability of microchips to counterfeiting poses a significant threat to nations, companies, and the general public. Creating a unique "fingerprint" on each chip using intrinsic manufacturing variations can significantly prevent the number of fraudulent chips. Since Si-based semiconductor fabrication processes are now flawless down to a few nanometers, finding a high-entropy source at the nanoscale has become challenging. Inspired by the concept of physical unclonable function, this work reports the CMOS-compatible and lithography-free fabrication of unique nanostructured silicon "fingerprints." Nanostructuring is achieved via low-temperature dewetting and metal-assisted chemical etching, which produces a high level of entropy and unique silicon-based nanoscale fingerprints with linewidths tunable from ≈8 to 140 nm, commensurate with the dimensions of mainstream microfabrication processes. These Si nanofingerprints are highly reliable for chip authentication and against reverse engineering, providing a large encoding capacity of up to 216384/µm2. For practical applications, detection of fingerprints protected with a polymer coating is demonstrated using back-scattered electron imaging.

Complimentary metal-oxide semiconductor (CMOS) integration of quantum technology provides a route to manufacture at volume, simplify assembly, reduce footprint, and increase performance. Quantum noise-limited homodyne detectors have applications across quantum technologies, and they comprise photonics and electronics. Here, we report a quantum noise-limited monolithic electronic-photonic integrated homodyne detector, with a footprint of 80 micrometers by 220 micrometers, fabricated in a 250-nanometer lithography bipolar CMOS process. We measure a 15.3-gigahertz 3-decibel bandwidth with a maximum shot noise clearance of 12 decibels and shot noise clearance out to 26.5 gigahertz, when measured with a 9-decibel-milliwatt power local oscillator. This performance is enabled by monolithic electronic-photonic integration, which goes below the capacitance limits of devices made up of separate integrated chips or discrete components. It exceeds the bandwidth of quantum detectors with macroscopic electronic interconnects, including wire and flip chip bonding. This demonstrates electronic-photonic integration enhancing quantum photonic device performance.

Semiconductor chip manufacturing is by far the predominant nanomanufacturing technology in the world today. Top-down lithography techniques are used for fabrication of logic and memory chips since, in order to function, these chips must essentially be perfect. Assuring perfection requires expensive metrology. Top of the line logic sells for several hundred thousand dollars per square metre and, even though the required metrology is expensive, it is a small percentage of the overall manufacturing cost. The level of stability and control afforded by current lithography tools means that much of this metrology can be online and statistical. In contrast, many of the novel types of nanomanufacturing currently being developed will produce products worth only a few dollars per square metre. To be cost effective, the required metrology must cost proportionately less. Fortunately many of these nanofabrication techniques, such as block copolymer self-assembly, colloidal self-assembly, DNA origami, roll-2-roll nano-imprint, etc., will not require the same level of perfection to meet specification. Given the variability of these self-assembly processes, in order to maintain process control, these techniques will require some level of real time online metrology. Hence we are led to the conclusion that future nanomanufacturing may well necessitate "cheap" nanometre scale metrology which functions real time and on-line, e.g. at GHz rates, in the production stream. In this paper we review top-down and bottom-up nanofabrication techniques and compare and contrast the various metrology requirements.

Optical-frequency synthesizers, which generate frequency-stable light from a single microwave-frequency reference, are revolutionizing ultrafast science and metrology, but their size, power requirement and cost need to be reduced if they are to be more widely used. Integrated-photonics microchips can be used in high-coherence applications, such as data transmission 1 , highly optimized physical sensors 2 and harnessing quantum states 3 , to lower cost and increase efficiency and portability. Here we describe a method for synthesizing the absolute frequency of a lightwave signal, using integrated photonics to create a phase-coherent microwave-to-optical link. We use a heterogeneously integrated III-V/silicon tunable laser, which is guided by nonlinear frequency combs fabricated on separate silicon chips and pumped by off-chip lasers. The laser frequency output of our optical-frequency synthesizer can be programmed by a microwave clock across 4 terahertz near 1,550 nanometres (the telecommunications C-band) with 1 hertz resolution. Our measurements verify that the output of the synthesizer is exceptionally stable across this region (synthesis error of 7.7 × 10-15 or below). Any application of an optical-frequency source could benefit from the high-precision optical synthesis presented here. Leveraging high-volume semiconductor processing built around advanced materials could allow such low-cost, low-power and compact integrated-photonics devices to be widely used.

Semiconductor surface patterning at the nanometer scale is crucial for high-performance optical, electronic, and photovoltaic devices. To date, surface nanostructures on organic-inorganic single-crystal perovskites have been achieved mainly through destructive methods such as electron-beam lithography and focused ion beam milling. Here, we present a solution-based epitaxial growth method for creating nanopatterns on the surface of perovskite monocrystalline thin films. We show that high-quality monocrystalline arbitrary nanopatterns can form in solution with a low-cost simple setup. We also demonstrate controllable photoluminescence from nanopatterned perovskite surfaces by adjusting the nanopattern parameters. A seven-fold enhancement in photoluminescence intensity and a three-time reduction of the surface radiative recombination lifetime are observed at room temperature for nanopatterned MAPbBr3 monocrystalline thin films. Our findings are promising for the cost-effective fabrication of monocrystalline perovskite on-chip electronic and photonic circuits down to the nanometer scale with finely tunable optoelectronic properties.

We demonstrate strain-controlled gratings made of an organic elastomer, polydimethylsiloxane (PDMS), which can achieve optical wavelength tuning by varying their spatial periods. The whole device structure presented in this work incorporates a nanoimprinted PDMS grating integrated with electrostatic microelectromechanical systems actuators on a silicon chip. The fabrication of the device combines polymer soft lithography, nanoimprint lithography, and silicon micromachining across multiscale dimensions ranging from a few hundred nanometers to a few millimeters. The fine tuning capability with fast dynamic response of our PDMS/silicon hybrid optical grating device makes it attractive for use in various micro-optical instruments.

In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

The ability to create controllable patterns of micro- and nanostructures on the surface of bulk silicon has widespread application potential. In particular, the direct writing of silicon oxide patterns on silicon via femtosecond laser-induced silicon amorphization has attracted considerable attention owing to its simplicity and high efficiency. However, the direct writing of nanoscale resolution is challenging due to the optical diffraction effect. In this study, we propose a highly efficient, one-step method for preparing silicon oxide nanopatterns on silicon. The proposed method combines femtosecond laser-induced silicon amorphization with a subwavelength-scale beam waist of photonic nanojets. We demonstrate the direct writing of arbitrary nanopatterns via contactless scanning, achieving patterns with a minimum feature size of 310 nm and a height of 120 nm. The proposed method shows potential for the fabrication of multifunctional surfaces, silicon-based chips, and silicon photonics.

The use of block copolymer self-assembly for device fabrication in the semiconductor industry has been envisioned for over a decade. Early works by the groups of Hawker, Russell, and Nealey [1-2] have shown a high degree of dimensional control of the self-assembled features over large areas with high degree of ordering. The exquisite dimensional control at nanometer-scale feature sizes is one of the most attractive properties of block copolymer self-assembly. At the same time, device and circuit fabrication for the semiconductor industry requires accurate placement of desired features at irregular positions on the chip. The need to coax the self-assembled features into circuit layout friendly location is a roadblock for introducing self-assembly into semiconductor manufacturing. Directed self-assembly (DSA) and the use of topography to direct the self-assembly (graphoepitaxy) have shown great promise in solving the placement problem [3-4]. In this paper, we review recent progress in using block copolymer directed self-assembly for patterning sub-20 nm contact holes for practical circuits.

An atom chip has been fabricated for the study of interactions between $^{87}$Rb Rydberg atoms and a Au surface. The chip tightly confines cold atoms by generating high magnetic field gradients using microfabricated current-carrying wires. These trapped atoms may be excited to Rydberg states at well-defined atom-surface distances. For the purpose of Rydberg atom-surface interaction studies, the chip has a thermally evaporated Au surface layer, separated from the underlying trapping wires by a planarizing polyimide dielectric. Special attention was paid to the edge roughness of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.

The interlayer spin correlations in the magnetic/non-magnetic semiconductor superlattices are reviewed. The experimental evidences of interlayer exchange coupling in different all-semiconductor structures, based on neutronographic and magnetic studies, are presented. A tight-binding model is used to explain interaction transfer across the non-magnetic block without the assistance of carriers in ferromagnetic EuS/PbS and antiferromagnetic EuTe/PbTe systems.

Building communication links among multiple users in a scalable and robust way is a key objective in achieving large-scale quantum networks. In realistic scenario, noise from the coexisting classical light is inevitable and can ultimately disrupt the entanglement. The previous significant fully connected multiuser entanglement distribution experiments are conducted using dark fiber links and there is no explicit relation between the entanglement degradations induced by classical noise and its error rate. Here we fabricate a semiconductor chip with a high figure-of-merit modal overlap to directly generate broadband polarization entanglement. Our monolithic source maintains polarization entanglement fidelity above 96% for 42 nm bandwidth with a brightness of 1.2*10^7 Hz/mW. We perform a continuously working quantum entanglement distribution among three users coexisting with classical light. Under finite-key analysis, we establish secure keys and enable images encryption as well as quantum secret sharing between users. Our work paves the way for practical multiparty quantum communication with integrated photonic architecture compatible with real-world fiber optical communication network.

The increasing complexity of modern very-large-scale integration (VLSI) design highlights the significance of Electronic Design Automation (EDA) technologies. Chip placement is a critical step in the EDA workflow, which positions chip modules on the canvas with the goal of optimizing performance, power, and area (PPA) metrics of final chip designs. Recent advances have demonstrated the great potential of AI-based algorithms in enhancing chip placement. However, due to the lengthy workflow of chip design, the evaluations of these algorithms often focus on intermediate surrogate metrics, which are easy to compute but frequently reveal a substantial misalignment with the end-to-end performance (i.e., the final design PPA). To address this challenge, we introduce ChiPBench, which can effectively facilitate research in chip placement within the AI community. ChiPBench is a comprehensive benchmark specifically designed to evaluate the effectiveness of existing AI-based chip placement algorithms in improving final design PPA metrics. Specifically, we have gathered 20 circuits from various domains (e.g., CPU, GPU, and microcontrollers). These designs are compiled by executing the workflow from the verilog source code, which preserves necessary physical implementation kits, enabling evaluations for the placement algorithms on their impacts on the final design PPA. We executed six state-of-the-art AI-based chip placement algorithms on these designs and plugged the results of each single-point algorithm into the physical implementation workflow to obtain the final PPA results. Experimental results show that even if intermediate metric of a single-point algorithm is dominant, while the final PPA results are unsatisfactory. We believe that our benchmark will serve as an effective evaluation framework to bridge the gap between academia and industry.

In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

Recently, there have been significant advances in the fabrication and demonstration of individual molecular electronic wires and diode switches. This paper reviews those developments and shows how demonstrated molecular devices might be combined to design molecular-scale electronic digital computer logic. The design for the demonstrated rectifying molecular diode switches is refined and made more compatible with the demonstrated wires through the introduction of intramolecular dopant groups chemically bonded to modified molecular wires. Quantum mechanical calculations are performed to characterize some of the electrical properties of the proposed molecular diode switches. Explicit structural designs are displayed for AND, OR, and XOR gates that are built from molecular wires and molecular diode switches. The diode-based molecular electronic logic gates are combined to produce a design for a molecular-scale electronic half adder and a molecular-scale electronic full adder. These designs correspond to conductive monomolecular circuit structures that would be one million times smaller in area than the corresponding micron-scale digital logic circuits fabricated on conventional solid-state semiconductor computer chips. It appears likely that these nanometer-scale molecular electronic logic circuits could be fabricated and tested in the foreseeable future. At the very least, such molecular circuit designs constitute an exploration of the ultimate limits of electronic computer circuit miniaturization.

Abstract Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance for advancing nanoscience and nanotechnology. While the capability of current complementary metal-oxide semiconductor (CMOS) chip manufacturing can produce structures on the sub-10 nm scale, many emerging applications, such as nano-optics, biosensing, and quantum devices, also require ultrasmall features down to single digital nanometers. In these emerging applications, CMOS-based manufacturing methods are currently not feasible or appropriate due to the considerations of usage cost, material compatibility, and exotic features. Therefore, several specific methods have been developed in the past decades for different applications. In this review, we attempt to give a systematic summary on sub-10 nm fabrication methods and their related applications. In the first and second parts, we give a brief introduction of the background of this research topic and explain why sub-10 nm fabrication is interesting from both scientific and technological perspectives. In the third part, we comprehensively summarize the fabrication methods and classify them into three main approaches, including lithographic, mechanics-enabled, and post-trimming processes. The fourth part discusses the applications of these processes in quantum devices, nano-optics, and high-performance sensing. Finally, a perspective is given to discuss the challenges and opportunities associated with this research topic.