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The development of micro- and nanotechnology for biomedical applications has defined the cutting edge of medical technology for over three decades, as advancements in fabrication technology developed originally in the semiconductor industry have been applied to solving ever-more complex problems in medicine and biology. These technologies are ideally suited to interfacing with life sciences, since they are on the scale lengths as cells (microns) and biomacromolecules (nanometers). In this paper, we review the state of the art in bionanotechnology and bioMEMS (collectively BNM), including developments and challenges in the areas of BNM, such as microfluidic organ-on-chip devices, oral drug delivery, emerging technologies for managing infectious diseases, 3D printed microfluidic devices, AC electrokinetics, flexible MEMS devices, implantable microdevices, paper-based microfluidic platforms for cellular analysis, and wearable sensors for point-of-care testing.

Two dimensional (2D) semiconductors have been established as promising candidates to break through the short channel effect that existed in Si metal-oxide-semiconductor field-effect-transistor (MOSFET), owing to their unique atomically layered structure and dangling-bond-free surface. The last decade has witnessed the significant progress in the size scaling of 2D transistors by various approaches, in which the physical gate length of the transistors has shrank from micrometer to sub-one nanometer with superior performance, illustrating their potential as a replacement technology for Si MOSFETs. Here, we review state-of-the-art techniques to achieve ultra-scaled 2D transistors with novel configurations through the scaling of channel, gate, and contact length. We provide comprehensive views of the merits and drawbacks of the ultra-scaled 2D transistors by summarizing the relevant fabrication processes with the corresponding critical parameters achieved. Finally, we identify the key opportunities and challenges for integrating ultra-scaled 2D transistors in the next-generation heterogeneous circuitry.

Complimentary metal-oxide semiconductor (CMOS) integration of quantum technology provides a route to manufacture at volume, simplify assembly, reduce footprint, and increase performance. Quantum noise-limited homodyne detectors have applications across quantum technologies, and they comprise photonics and electronics. Here, we report a quantum noise-limited monolithic electronic-photonic integrated homodyne detector, with a footprint of 80 micrometers by 220 micrometers, fabricated in a 250-nanometer lithography bipolar CMOS process. We measure a 15.3-gigahertz 3-decibel bandwidth with a maximum shot noise clearance of 12 decibels and shot noise clearance out to 26.5 gigahertz, when measured with a 9-decibel-milliwatt power local oscillator. This performance is enabled by monolithic electronic-photonic integration, which goes below the capacitance limits of devices made up of separate integrated chips or discrete components. It exceeds the bandwidth of quantum detectors with macroscopic electronic interconnects, including wire and flip chip bonding. This demonstrates electronic-photonic integration enhancing quantum photonic device performance.

Wafer-scale fabrication of complex nanofluidic systems with integrated electronics is essential to realizing ubiquitous, compact, reliable, high-sensitivity and low-cost biomolecular sensors. Here we report a scalable fabrication strategy capable of producing nanofluidic chips with complex designs and down to single-digit nanometre dimensions over 200 mm wafer scale. Compatible with semiconductor industry standard complementary metal-oxide semiconductor logic circuit fabrication processes, this strategy extracts a patterned sacrificial silicon layer through hundreds of millions of nanoscale vent holes on each chip by gas-phase Xenon difluoride etching. Using single-molecule fluorescence imaging, we demonstrate these sacrificial nanofluidic chips can function to controllably and completely stretch lambda DNA in a two-dimensional nanofluidic network comprising channels and pillars. The flexible nanofluidic structure design, wafer-scale fabrication, single-digit nanometre channels, reliable fluidic sealing and low thermal budget make our strategy a potentially universal approach to integrating functional planar nanofluidic systems with logic circuits for lab-on-a-chip applications.

Optical-frequency synthesizers, which generate frequency-stable light from a single microwave-frequency reference, are revolutionizing ultrafast science and metrology, but their size, power requirement and cost need to be reduced if they are to be more widely used. Integrated-photonics microchips can be used in high-coherence applications, such as data transmission 1 , highly optimized physical sensors 2 and harnessing quantum states 3 , to lower cost and increase efficiency and portability. Here we describe a method for synthesizing the absolute frequency of a lightwave signal, using integrated photonics to create a phase-coherent microwave-to-optical link. We use a heterogeneously integrated III-V/silicon tunable laser, which is guided by nonlinear frequency combs fabricated on separate silicon chips and pumped by off-chip lasers. The laser frequency output of our optical-frequency synthesizer can be programmed by a microwave clock across 4 terahertz near 1,550 nanometres (the telecommunications C-band) with 1 hertz resolution. Our measurements verify that the output of the synthesizer is exceptionally stable across this region (synthesis error of 7.7 × 10-15 or below). Any application of an optical-frequency source could benefit from the high-precision optical synthesis presented here. Leveraging high-volume semiconductor processing built around advanced materials could allow such low-cost, low-power and compact integrated-photonics devices to be widely used.

Semiconductor chip manufacturing is by far the predominant nanomanufacturing technology in the world today. Top-down lithography techniques are used for fabrication of logic and memory chips since, in order to function, these chips must essentially be perfect. Assuring perfection requires expensive metrology. Top of the line logic sells for several hundred thousand dollars per square metre and, even though the required metrology is expensive, it is a small percentage of the overall manufacturing cost. The level of stability and control afforded by current lithography tools means that much of this metrology can be online and statistical. In contrast, many of the novel types of nanomanufacturing currently being developed will produce products worth only a few dollars per square metre. To be cost effective, the required metrology must cost proportionately less. Fortunately many of these nanofabrication techniques, such as block copolymer self-assembly, colloidal self-assembly, DNA origami, roll-2-roll nano-imprint, etc., will not require the same level of perfection to meet specification. Given the variability of these self-assembly processes, in order to maintain process control, these techniques will require some level of real time online metrology. Hence we are led to the conclusion that future nanomanufacturing may well necessitate "cheap" nanometre scale metrology which functions real time and on-line, e.g. at GHz rates, in the production stream. In this paper we review top-down and bottom-up nanofabrication techniques and compare and contrast the various metrology requirements.

Metachips are formed by incorporating periodically arranged meta-atoms with on-chip circuits, enabling electromagnetic wave manipulation at the single-chip-tile level and holding great promise for terahertz applications. In this work, we present a complementary metal-oxide semiconductor (CMOS)-based terahertz-programmable metachip and demonstrate its proof of concept for terahertz-integrated sensing and communication (T-ISAC) with array scalability. Fabricated using an industry-standard 55-nanometer CMOS process, the proposed metachip realizes terahertz wave modulation at dual frequencies near 410 and 520 gigahertz in both reflection and transmission (transflection) modes. The metachip array supports multichannel terahertz communication by addressing distinct modulation signals to each chip tile. By harnessing the array scalability, the metachip array facilitates motion tracking of metallic objects while enabling the detection of the terahertz fingerprint material α-lactose against glucose. The proposed CMOS metachip represents a viable pathway toward integrated system-on-chip terahertz hardware solutions for scalable T-ISAC applications.

The increasing vulnerability of microchips to counterfeiting poses a significant threat to nations, companies, and the general public. Creating a unique "fingerprint" on each chip using intrinsic manufacturing variations can significantly prevent the number of fraudulent chips. Since Si-based semiconductor fabrication processes are now flawless down to a few nanometers, finding a high-entropy source at the nanoscale has become challenging. Inspired by the concept of physical unclonable function, this work reports the CMOS-compatible and lithography-free fabrication of unique nanostructured silicon "fingerprints." Nanostructuring is achieved via low-temperature dewetting and metal-assisted chemical etching, which produces a high level of entropy and unique silicon-based nanoscale fingerprints with linewidths tunable from ≈8 to 140 nm, commensurate with the dimensions of mainstream microfabrication processes. These Si nanofingerprints are highly reliable for chip authentication and against reverse engineering, providing a large encoding capacity of up to 216384/µm2. For practical applications, detection of fingerprints protected with a polymer coating is demonstrated using back-scattered electron imaging.

The characterization of nanometer CMOS transistors of different aspect ratios at deep-cryogenic temperatures (4 K and 100 mK) is presented for two standard CMOS technologies (40 nm and 160 nm). A detailed understanding of the device physics at those temperatures was developed and captured in an augmented MOS11/PSP model. The accuracy of the proposed model is demonstrated by matching simulations and measurements for DC and time-domain at 4 K and, for the first time, at 100 mK.

In an SRAM circuit, the leakage currents on the bit lines are getting increasingly prominent with the dwindling of transistors' threshold voltages as the technology scales down to 90 nm and beyond. Excessive bit-line leakage current results in slower read operations or even functional failure. In this paper, we present a new technique, called X-calibration, to combat this phenomenon. Unlike the previous method that attempts to compensate the leakage current directly, this scheme first transforms the bit-line leakage current into an equilibrium offset voltage across the bit-line pair, and then simple circuitry is utilized to cancel this offset accurately at the input of the sense amplifier so that the sensing is not affected by the bit-line leakage. SPICE simulation of a 1 Kbit SRAM macro shows that this X-calibration scheme can handle 83% higher bit-line leakage current than the previous bit-line leakage compensation scheme. Measurement results of the test chip show that the SRAM macro adopting X-calibration scheme can cope with up to 320 <inline-formula><tex-math>$\mu{\hbox{A}}$</tex-math></inline-formula> bit-line leakage current.

We demonstrate strain-controlled gratings made of an organic elastomer, polydimethylsiloxane (PDMS), which can achieve optical wavelength tuning by varying their spatial periods. The whole device structure presented in this work incorporates a nanoimprinted PDMS grating integrated with electrostatic microelectromechanical systems actuators on a silicon chip. The fabrication of the device combines polymer soft lithography, nanoimprint lithography, and silicon micromachining across multiscale dimensions ranging from a few hundred nanometers to a few millimeters. The fine tuning capability with fast dynamic response of our PDMS/silicon hybrid optical grating device makes it attractive for use in various micro-optical instruments.

Recently, there have been significant advances in the fabrication and demonstration of individual molecular electronic wires and diode switches. This paper reviews those developments and shows how demonstrated molecular devices might be combined to design molecular-scale electronic digital computer logic. The design for the demonstrated rectifying molecular diode switches is refined and made more compatible with the demonstrated wires through the introduction of intramolecular dopant groups chemically bonded to modified molecular wires. Quantum mechanical calculations are performed to characterize some of the electrical properties of the proposed molecular diode switches. Explicit structural designs are displayed for AND, OR, and XOR gates that are built from molecular wires and molecular diode switches. The diode-based molecular electronic logic gates are combined to produce a design for a molecular-scale electronic half adder and a molecular-scale electronic full adder. These designs correspond to conductive monomolecular circuit structures that would be one million times smaller in area than the corresponding micron-scale digital logic circuits fabricated on conventional solid-state semiconductor computer chips. It appears likely that these nanometer-scale molecular electronic logic circuits could be fabricated and tested in the foreseeable future. At the very least, such molecular circuit designs constitute an exploration of the ultimate limits of electronic computer circuit miniaturization.

An atom chip has been fabricated for the study of interactions between $^{87}$Rb Rydberg atoms and a Au surface. The chip tightly confines cold atoms by generating high magnetic field gradients using microfabricated current-carrying wires. These trapped atoms may be excited to Rydberg states at well-defined atom-surface distances. For the purpose of Rydberg atom-surface interaction studies, the chip has a thermally evaporated Au surface layer, separated from the underlying trapping wires by a planarizing polyimide dielectric. Special attention was paid to the edge roughness of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.

The interlayer spin correlations in the magnetic/non-magnetic semiconductor superlattices are reviewed. The experimental evidences of interlayer exchange coupling in different all-semiconductor structures, based on neutronographic and magnetic studies, are presented. A tight-binding model is used to explain interaction transfer across the non-magnetic block without the assistance of carriers in ferromagnetic EuS/PbS and antiferromagnetic EuTe/PbTe systems.

Building communication links among multiple users in a scalable and robust way is a key objective in achieving large-scale quantum networks. In realistic scenario, noise from the coexisting classical light is inevitable and can ultimately disrupt the entanglement. The previous significant fully connected multiuser entanglement distribution experiments are conducted using dark fiber links and there is no explicit relation between the entanglement degradations induced by classical noise and its error rate. Here we fabricate a semiconductor chip with a high figure-of-merit modal overlap to directly generate broadband polarization entanglement. Our monolithic source maintains polarization entanglement fidelity above 96% for 42 nm bandwidth with a brightness of 1.2*10^7 Hz/mW. We perform a continuously working quantum entanglement distribution among three users coexisting with classical light. Under finite-key analysis, we establish secure keys and enable images encryption as well as quantum secret sharing between users. Our work paves the way for practical multiparty quantum communication with integrated photonic architecture compatible with real-world fiber optical communication network.

In this article, we proposed a programmable 16-channel photonic solver for quadratic unconstrained binary optimization (QUBO) problems. The solver is based on a hybrid optoelectronic scheme including a photonic chip and the corresponding electronic driving circuit. The photonic chip is fabricated on silicon on insulator (SOI) substrate and integrates high-speed electro-optic modulators, thermo-optic phase shifters and photodetectors to conduct the 16-dimensional optical vector-matrix multiplication (OVMM). Due to the parallel and low latency propagation of lightwave, the calculation of the QUBO cost function can be accelerated. Besides, the electronic processor is employed to run the heuristic algorithm to search the optimal solution. In the experiment, two 16-dimensional randomly generated QUBO problems are solved with high successful probabilities. To our knowledge, it is the largest scale of programmable and on-chip photonic solver ever reported. Moreover, the computing speed of the OVMM on photonic chip is ~2 TFLOP/s. It shows the potential of fast solving such optimization problems with integrated photonic systems.

From the ACS meeting Electronic semiconductor devices are ubiquitous—from computers to cars to industrial process control. At a symposium on polymers for micropatterning and nanopatterning sponsored by the Division of Polymeric Materials: Science & Engineering, chemists reported progress in the fabrication of such devices. Their progress will make possible the data-processing units and memory chips of the future. A key semiconductor fabrication technology is microlithography—the etching, doping, and plating of devices onto semiconductor surfaces at resolutions of micrometers to nanometers. Achieving ever-finer patterns—needed for smaller and faster devices—depends on polymeric resins called photoresists. It became clear during the symposium that microlithography might eventually be superseded by advances in new technologies—"drawing" of patterns on resist layers by electron beams, for example, or "printing," "rubberstamping," or molding of images at exquisitely fine resolution onto semiconductor surfaces. But as several sessions made clear, advances are still being made in microlithography at the finer resolutions made possible by ...

This article describes the systemic problem of the development of the Russian semiconductor industry due to the lack of national production of integrated microcircuits with topological standards below 65 nm. Here are the results of the analysis of the feasibility of production lines of integrated circuits developing, depending on the forecasted volume of demand for various categories of semiconductor products, the technological backlog of Russian organizations and the estimated cost of the project. In this article, there are suggestions on possible sources of project financing and measures of non-financial support. Also, it describes the general technological parameters of the created production. It contains an assessment of key performance indicators of the project and the impact of its implementation on related technological areas.

Semiconductor chips underpin modern electronics, yet conventional design and fabrication methods face escalating costs and diminishing returns as device geometries shrink. This review surveys the integration of artificial intelligence (AI) across chip development workflows, categorizing methodologies into supervised machine learning (e.g., SVM, decision trees), deep learning (CNN, RNN/LSTM/GRU, GAN), other AI paradigms (reinforcement, active, transfer learning; genetic algorithms; Bayesian optimization), and hybrid frameworks. In chip design, AI accelerates layout optimization, power‐performance trade‐off, and defect classification, while in fabrication it enhances wafer‐level defect detection, process monitoring, and production scheduling. Case studies illustrate GAN–CNN hybrids for noise‐robust fault diagnosis and GA–SVM/DT pipelines for failure prediction. Despite notable successes—such as sub‐nanometer feature prediction and real‐time anomaly detection—key challenges persist: scarcity of high‐quality, labeled datasets due to proprietary restrictions; the “black‐box” nature of deep models impeding interpretability; and a shortage of interdisciplinary expertise bridging AI and semiconductor domains. Future research should prioritize development of explainable models, federated or synthetic data generation strategies, and cross‐domain education to cultivate hybrid talent.

Transition metal doped semiconductor nanostructure materials (Sb2O3 doped ZnO microflowers, MFs) are deposited onto tiny µ-chip (surface area, ∼0.02217 cm(2)) to fabricate a smart chemical sensor for toxic ethanol in phosphate buffer solution (0.1 M PBS). The fabricated chemi-sensor is also exhibited higher sensitivity, large-dynamic concentration ranges, long-term stability, and improved electrochemical performances towards ethanol. The calibration plot is linear (r(2) = 0.9989) over the large ethanol concentration ranges (0.17 mM to 0.85 M). The sensitivity and detection limit is ∼5.845 µAcm(-2)mM(-1) and ∼0.11±0.02 mM (signal-to-noise ratio, at a SNR of 3) respectively. Here, doped MFs are prepared by a wet-chemical process using reducing agents in alkaline medium, which characterized by UV/vis., FT-IR, Raman, X-ray photoelectron spectroscopy (XPS), powder X-ray diffraction (XRD), and field-emission scanning electron microscopy (FE-SEM) etc. The fabricated ethanol chemical sensor using Sb2O3-ZnO MFs is simple, reliable, low-sample volume (<70.0 µL), easy of integration, high sensitivity, and excellent stability for the fabrication of efficient I-V sensors on μ-chips.