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We demonstrate strain-controlled gratings made of an organic elastomer, polydimethylsiloxane (PDMS), which can achieve optical wavelength tuning by varying their spatial periods. The whole device structure presented in this work incorporates a nanoimprinted PDMS grating integrated with electrostatic microelectromechanical systems actuators on a silicon chip. The fabrication of the device combines polymer soft lithography, nanoimprint lithography, and silicon micromachining across multiscale dimensions ranging from a few hundred nanometers to a few millimeters. The fine tuning capability with fast dynamic response of our PDMS/silicon hybrid optical grating device makes it attractive for use in various micro-optical instruments.

Recently, there have been significant advances in the fabrication and demonstration of individual molecular electronic wires and diode switches. This paper reviews those developments and shows how demonstrated molecular devices might be combined to design molecular-scale electronic digital computer logic. The design for the demonstrated rectifying molecular diode switches is refined and made more compatible with the demonstrated wires through the introduction of intramolecular dopant groups chemically bonded to modified molecular wires. Quantum mechanical calculations are performed to characterize some of the electrical properties of the proposed molecular diode switches. Explicit structural designs are displayed for AND, OR, and XOR gates that are built from molecular wires and molecular diode switches. The diode-based molecular electronic logic gates are combined to produce a design for a molecular-scale electronic half adder and a molecular-scale electronic full adder. These designs correspond to conductive monomolecular circuit structures that would be one million times smaller in area than the corresponding micron-scale digital logic circuits fabricated on conventional solid-state semiconductor computer chips. It appears likely that these nanometer-scale molecular electronic logic circuits could be fabricated and tested in the foreseeable future. At the very least, such molecular circuit designs constitute an exploration of the ultimate limits of electronic computer circuit miniaturization.

In this paper we present practical techniques that enable diagnosis of defective library cells in a failing die. Our technique can handle large industrial designs and practical situations like compressed test patterns with multiple exercising conditions per pattern and sequence dependent defects. Being able to accurately differentiate between cell-internal and interconnect defects leads to a faster root cause failure analysis at a reduced cost. This capability was applied on an AMD graphics chip using 90nm at TSMC. In all of the failing dies that underwent physical failure analysis, the defective library cell identified by diagnosis was verified to be correct by failure analysis. Currently this capability is successfully used to diagnose another design using TSMC's 65nm technology.

In the next decade, advances in complementary metal-oxide semiconductor fabrication will lead to devices with gate lengths (the region in the device that switches the current flow on and off) below 10 nanometers (nm), as compared with current gate lengths in chips that are now about 50 nm. However, conventional scaling will no longer be sufficient to continue device performance by creating smaller transistors. Alternatives that are being pursued include new device geometries such as ultrathin channel structures to control capacitive losses and multiple gates to better control leakage pathways. Improvement in device speed by enhancing the mobility of charge carriers may be obtained with strain engineering and the use of different crystal orientations. Here, we discuss challenges and possible solutions for continued silicon device performance trends down to the sub-10-nm gate regimes.

An atom chip has been fabricated for the study of interactions between $^{87}$Rb Rydberg atoms and a Au surface. The chip tightly confines cold atoms by generating high magnetic field gradients using microfabricated current-carrying wires. These trapped atoms may be excited to Rydberg states at well-defined atom-surface distances. For the purpose of Rydberg atom-surface interaction studies, the chip has a thermally evaporated Au surface layer, separated from the underlying trapping wires by a planarizing polyimide dielectric. Special attention was paid to the edge roughness of the trapping wires, the planarization of the polyimide, and the grain structure of the Au surface.

The interlayer spin correlations in the magnetic/non-magnetic semiconductor superlattices are reviewed. The experimental evidences of interlayer exchange coupling in different all-semiconductor structures, based on neutronographic and magnetic studies, are presented. A tight-binding model is used to explain interaction transfer across the non-magnetic block without the assistance of carriers in ferromagnetic EuS/PbS and antiferromagnetic EuTe/PbTe systems.

Building communication links among multiple users in a scalable and robust way is a key objective in achieving large-scale quantum networks. In realistic scenario, noise from the coexisting classical light is inevitable and can ultimately disrupt the entanglement. The previous significant fully connected multiuser entanglement distribution experiments are conducted using dark fiber links and there is no explicit relation between the entanglement degradations induced by classical noise and its error rate. Here we fabricate a semiconductor chip with a high figure-of-merit modal overlap to directly generate broadband polarization entanglement. Our monolithic source maintains polarization entanglement fidelity above 96% for 42 nm bandwidth with a brightness of 1.2*10^7 Hz/mW. We perform a continuously working quantum entanglement distribution among three users coexisting with classical light. Under finite-key analysis, we establish secure keys and enable images encryption as well as quantum secret sharing between users. Our work paves the way for practical multiparty quantum communication with integrated photonic architecture compatible with real-world fiber optical communication network.

In this article, we proposed a programmable 16-channel photonic solver for quadratic unconstrained binary optimization (QUBO) problems. The solver is based on a hybrid optoelectronic scheme including a photonic chip and the corresponding electronic driving circuit. The photonic chip is fabricated on silicon on insulator (SOI) substrate and integrates high-speed electro-optic modulators, thermo-optic phase shifters and photodetectors to conduct the 16-dimensional optical vector-matrix multiplication (OVMM). Due to the parallel and low latency propagation of lightwave, the calculation of the QUBO cost function can be accelerated. Besides, the electronic processor is employed to run the heuristic algorithm to search the optimal solution. In the experiment, two 16-dimensional randomly generated QUBO problems are solved with high successful probabilities. To our knowledge, it is the largest scale of programmable and on-chip photonic solver ever reported. Moreover, the computing speed of the OVMM on photonic chip is ~2 TFLOP/s. It shows the potential of fast solving such optimization problems with integrated photonic systems.

From the ACS meeting Electronic semiconductor devices are ubiquitous—from computers to cars to industrial process control. At a symposium on polymers for micropatterning and nanopatterning sponsored by the Division of Polymeric Materials: Science & Engineering, chemists reported progress in the fabrication of such devices. Their progress will make possible the data-processing units and memory chips of the future. A key semiconductor fabrication technology is microlithography—the etching, doping, and plating of devices onto semiconductor surfaces at resolutions of micrometers to nanometers. Achieving ever-finer patterns—needed for smaller and faster devices—depends on polymeric resins called photoresists. It became clear during the symposium that microlithography might eventually be superseded by advances in new technologies—"drawing" of patterns on resist layers by electron beams, for example, or "printing," "rubberstamping," or molding of images at exquisitely fine resolution onto semiconductor surfaces. But as several sessions made clear, advances are still being made in microlithography at the finer resolutions made possible by ...

This article describes the systemic problem of the development of the Russian semiconductor industry due to the lack of national production of integrated microcircuits with topological standards below 65 nm. Here are the results of the analysis of the feasibility of production lines of integrated circuits developing, depending on the forecasted volume of demand for various categories of semiconductor products, the technological backlog of Russian organizations and the estimated cost of the project. In this article, there are suggestions on possible sources of project financing and measures of non-financial support. Also, it describes the general technological parameters of the created production. It contains an assessment of key performance indicators of the project and the impact of its implementation on related technological areas.

Transition metal doped semiconductor nanostructure materials (Sb2O3 doped ZnO microflowers, MFs) are deposited onto tiny µ-chip (surface area, ∼0.02217 cm(2)) to fabricate a smart chemical sensor for toxic ethanol in phosphate buffer solution (0.1 M PBS). The fabricated chemi-sensor is also exhibited higher sensitivity, large-dynamic concentration ranges, long-term stability, and improved electrochemical performances towards ethanol. The calibration plot is linear (r(2) = 0.9989) over the large ethanol concentration ranges (0.17 mM to 0.85 M). The sensitivity and detection limit is ∼5.845 µAcm(-2)mM(-1) and ∼0.11±0.02 mM (signal-to-noise ratio, at a SNR of 3) respectively. Here, doped MFs are prepared by a wet-chemical process using reducing agents in alkaline medium, which characterized by UV/vis., FT-IR, Raman, X-ray photoelectron spectroscopy (XPS), powder X-ray diffraction (XRD), and field-emission scanning electron microscopy (FE-SEM) etc. The fabricated ethanol chemical sensor using Sb2O3-ZnO MFs is simple, reliable, low-sample volume (<70.0 µL), easy of integration, high sensitivity, and excellent stability for the fabrication of efficient I-V sensors on μ-chips.

Semiconductor chips underpin modern electronics, yet conventional design and fabrication methods face escalating costs and diminishing returns as device geometries shrink. This review surveys the integration of artificial intelligence (AI) across chip development workflows, categorizing methodologies into supervised machine learning (e.g., SVM, decision trees), deep learning (CNN, RNN/LSTM/GRU, GAN), other AI paradigms (reinforcement, active, transfer learning; genetic algorithms; Bayesian optimization), and hybrid frameworks. In chip design, AI accelerates layout optimization, power‐performance trade‐off, and defect classification, while in fabrication it enhances wafer‐level defect detection, process monitoring, and production scheduling. Case studies illustrate GAN–CNN hybrids for noise‐robust fault diagnosis and GA–SVM/DT pipelines for failure prediction. Despite notable successes—such as sub‐nanometer feature prediction and real‐time anomaly detection—key challenges persist: scarcity of high‐quality, labeled datasets due to proprietary restrictions; the “black‐box” nature of deep models impeding interpretability; and a shortage of interdisciplinary expertise bridging AI and semiconductor domains. Future research should prioritize development of explainable models, federated or synthetic data generation strategies, and cross‐domain education to cultivate hybrid talent.