{"technology":{"slug":"semiconductor","name":"Semiconductor Technology","description":"Advanced semiconductor manufacturing and design. Covers chip fabrication below 3nm, EUV lithography, novel materials, chiplet architectures, and neuromorphic computing.","discipline":"Engineering / Materials Science","icon":"💻"},"lastUpdated":"2026-10-06T11:10:29.274Z","articleCount":15,"articles":[{"id":"oa-W2757913998","title":"Nanoimprint lithography steppers for volume fabrication of leading-edge semiconductor integrated circuits","authors":"S. V. Sreenivasan","journal":"Microsystems & Nanoengineering","pubDate":"2017-09-25","doi":"10.1038/micronano.2017.75","abstract":"This article discusses the transition of a form of nanoimprint lithography technology, known as Jet and Flash Imprint Lithography (J-FIL), from research to a commercial fabrication infrastructure for leading-edge semiconductor integrated circuits (ICs). Leading-edge semiconductor lithography has some of the most aggressive technology requirements, and has been a key driver in the 50-year history of semiconductor scaling. Introducing a new, disruptive capability into this arena is therefore a case study in a \"high-risk-high-reward\" opportunity. This article first discusses relevant literature in nanopatterning including advanced lithography options that have been explored by the IC fabrication industry, novel research ideas being explored, and literature in nanoimprint lithography. The article then focuses on the J-FIL process, and the interdisciplinary nature of risk, involving nanoscale precision systems, mechanics, materials, material delivery systems, contamination control, and process engineering. Next, the article discusses the strategic decisions that were made in the early phases of the project including: (i) choosing a step and repeat process approach; (ii) identifying the first target IC market for J-FIL; (iii) defining the product scope and the appropriate collaborations to share the risk-reward landscape; and (iv) properly leveraging existing infrastructure, including minimizing disruption to the widely accepted practices in photolithography. Finally, the paper discusses the commercial J-FIL stepper system and associated infrastructure, and the resulting advances in the key lithographic process metrics such as critical dimension control, overlay, throughput, process defects, and electrical yield over the past 5 years. This article concludes with the current state of the art in J-FIL technology for IC fabrication, including description of the high volume manufacturing stepper tools created for advanced memory manufacturing.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2757913998","citationCount":229,"isOpenAccess":true,"pdfUrl":"https://www.nature.com/articles/micronano201775.pdf"},{"id":"oa-W3166690669","title":"Sub-10 nm fabrication: methods and applications","authors":"Yiqin Chen, Zhiwen Shu, Shi Zhang, Pei Zeng, Huikang Liang, Mengjie Zheng, Huigao Duan","journal":"International Journal of Extreme Manufacturing","pubDate":"2021-06-04","doi":"10.1088/2631-7990/ac087c","abstract":"Abstract Reliable fabrication of micro/nanostructures with sub-10 nm features is of great significance for advancing nanoscience and nanotechnology. While the capability of current complementary metal-oxide semiconductor (CMOS) chip manufacturing can produce structures on the sub-10 nm scale, many emerging applications, such as nano-optics, biosensing, and quantum devices, also require ultrasmall features down to single digital nanometers. In these emerging applications, CMOS-based manufacturing methods are currently not feasible or appropriate due to the considerations of usage cost, material compatibility, and exotic features. Therefore, several specific methods have been developed in the past decades for different applications. In this review, we attempt to give a systematic summary on sub-10 nm fabrication methods and their related applications. In the first and second parts, we give a brief introduction of the background of this research topic and explain why sub-10 nm fabrication is interesting from both scientific and technological perspectives. In the third part, we comprehensively summarize the fabrication methods and classify them into three main approaches, including lithographic, mechanics-enabled, and post-trimming processes. The fourth part discusses the applications of these processes in quantum devices, nano-optics, and high-performance sensing. Finally, a perspective is given to discuss the challenges and opportunities associated with this research topic.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W3166690669","citationCount":209,"isOpenAccess":true,"pdfUrl":"https://iopscience.iop.org/article/10.1088/2631-7990/ac087c/pdf"},{"id":"oa-W2744977531","title":"On-chip growth of semiconductor metal oxide nanowires for gas sensors: A review","authors":"Chu Manh Hung, Dang Thi Thanh Le, Nguyen Van Hieu","journal":"Journal of Science Advanced Materials and Devices","pubDate":"2017-08-12","doi":"10.1016/j.jsamd.2017.07.009","abstract":"Semiconductor metal oxide nanowires (SMO-NWs) show great potential for novel gas sensor applications because of their distinct properties, such as a high surface area to volume aspect ratio, high crystallinity and perfect pathway for electron transfer (length of NW). SMO-NW sensors can be configured as resistors or field-effect transistors for gas detection and different configurations, such as a single NW, multiple NWs, and networked NW films, have been established. Surface-functionalizing NWs with catalyst elements and self-heating NWs provide additional advantages for highly selective and low-power consumption gas sensors. However, an appropriate design of SMO-NWs is of practical importance in enhancing the gas-sensing performance of SMO-NW sensors. The on-chip growth of SMO-NWs possesses many advantages which can thus be effectively used for the large-scale fabrication of SMO-NW sensors with improved gas response and stability. This review aims to provide up-to-date information on the on-chip fabrication of SnO 2 , ZnO, WO 3 , CuO, and other SMO-NW sensors. It also discusses a variety of promising approaches that help advance the on-chip fabrication of SMO-NW-based gas sensors and other NW-based devices.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2744977531","citationCount":109,"isOpenAccess":true,"pdfUrl":"https://www.sciencedirect.com/science/article/pii/S2468217917301302/pdf"},{"id":"oa-W2982544440","title":"Semiconductor nanowire plasmonic lasers","authors":"Chun Li, Zhen Liu, Jie Chen, Yan Na Gao, Meili Li, Qing Zhang","journal":"Nanophotonics","pubDate":"2018-06-01","doi":"10.1515/nanoph-2019-0206","abstract":"Abstract Semiconductor nanowires (NW) hold great promise for micro/nanolasers owing to their naturally formed resonant microcavity, tightly confined electromagnetic field, and outstanding capability of integration with planar waveguide for on‐chip optoelectronic applications. However, constrained by the optical diffraction limit, the dimension of semiconductor lasers cannot be smaller than half the optical wavelength in free space, typically several hundreds of nanometers. Semiconductor NW plasmonic lasers provide a solution to break this limitation and realize deep sub‐wavelength light sources. In this review, we summarize the advances of semiconductor NW plasmonic lasers since their first demonstration in 2009. First of all, we briefly look into the fabrication and physical/chemical properties of semiconductor NWs. Next, we discuss the fundamentals of surface plasmons as well as the recent progress in semiconductor NW plasmonic lasers from the aspects of multicolor realization, threshold reduction, ultrafast modulation, and electrically driven operations, along with their applications in sensing and integrated optics. Finally, we provide insights into bright perspectives and remaining challenges.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2982544440","citationCount":48,"isOpenAccess":true,"pdfUrl":"https://doi.org/10.1515/nanoph-2019-0206"},{"id":"oa-W2028530049","title":"Fabrication of Smart Chemical Sensors Based on Transition-Doped-Semiconductor Nanostructure Materials with µ-Chips","authors":"Mohammed Muzibur Rahman, Sher Bahadar Khan, Abdullah Mohamed Asiri","journal":"PLoS ONE","pubDate":"2014-01-13","doi":"10.1371/journal.pone.0085036","abstract":"Transition metal doped semiconductor nanostructure materials (Sb2O3 doped ZnO microflowers, MFs) are deposited onto tiny µ-chip (surface area, ∼0.02217 cm(2)) to fabricate a smart chemical sensor for toxic ethanol in phosphate buffer solution (0.1 M PBS). The fabricated chemi-sensor is also exhibited higher sensitivity, large-dynamic concentration ranges, long-term stability, and improved electrochemical performances towards ethanol. The calibration plot is linear (r(2) = 0.9989) over the large ethanol concentration ranges (0.17 mM to 0.85 M). The sensitivity and detection limit is ∼5.845 µAcm(-2)mM(-1) and ∼0.11±0.02 mM (signal-to-noise ratio, at a SNR of 3) respectively. Here, doped MFs are prepared by a wet-chemical process using reducing agents in alkaline medium, which characterized by UV/vis., FT-IR, Raman, X-ray photoelectron spectroscopy (XPS), powder X-ray diffraction (XRD), and field-emission scanning electron microscopy (FE-SEM) etc. The fabricated ethanol chemical sensor using Sb2O3-ZnO MFs is simple, reliable, low-sample volume (<70.0 µL), easy of integration, high sensitivity, and excellent stability for the fabrication of efficient I-V sensors on μ-chips.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2028530049","citationCount":37,"isOpenAccess":true,"pdfUrl":"https://journals.plos.org/plosone/article/file?id=10.1371/journal.pone.0085036&type=printable"},{"id":"oa-W2049562185","title":"Fabrication of Semiconductor Nanowires for Electronic Transport Measurements","authors":"A. Pfund, Ivan Shorubalko, Renaud Leturcq, Magnus T. Borgström, Fabian Gramm, Elisabeth A. Müller, K. Ensslin","journal":"CHIMIA International Journal for Chemistry","pubDate":"2006-11-29","doi":"10.2533/chimia.2006.729","abstract":"We report on epitaxial growth of InAs nanowires and the steps necessary to create devices for electrnic transport experiments. Growth conditions were found by the use of metal organic vapor phase epitaxy (MOVPE) resulting in nanowires with designable length and diameter. Electrical properties indicate diffusive electron transport with an elastic mean free path of around hundred nanometers. Coherent quantum mechanical effects and single electron tunneling can be observed at low temperatures in quantum dots created along the nanowire. We demonstrate the realization of highly tunable quantum dots with metallic top-gates. Beyond that, alternative techniques to introduce potential barriers based on local constrictions are investigated.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2049562185","citationCount":22,"isOpenAccess":true,"pdfUrl":"https://chimia.ch/chimia/article/download/4238/3528"},{"id":"oa-W2025264359","title":"Electrodeposition for the Fabrication of Copper Interconnection in Semiconductor Devices","authors":"Myung Jun Kim, Jae Jeong Kim","journal":"Korean Chemical Engineering Research","pubDate":"2014-02-01","doi":"10.9713/kcer.2014.52.1.26","abstract":"전자 소자의 구리 금속 배선은 전해 도금을 포함한 다마신 공정을 통해 형성한다. 본 총설에서는 배선 형성을 위한 구리 전해 도금 및 수퍼필링 메카니즘에 대해 다루고자 한다. 수퍼필링 기술은 전해 도금의 전해질에 포함된 유기 첨가제의 영향에 의한 결과이며, 이는 유기 첨가제의 표면 덮임율을 조절하여 웨이퍼 위에 형성된 패턴의 바닥 면에서의 전해 도금 속도를 선택적으로 높임으로써 가능하다. 소자의 집적도를 높이기 위해 금속 배선의 크기는 계속적으로 감소하여 현재 그 폭이 수십 nm 수준으로 줄어들었다. 이러한 배선 폭의 감소는 구리 배선의 전기적 특성 감소, 신뢰성의 저하, 그리고 수퍼필링의 어려움 등 여러 가지 문제를 야기하고 있다. 본 총설에서는 상기 기술한 문제점을 해결하기 위해 구리의 미세 구조 개선을 위한 첨가제의 개발, 펄스 및 펄스-리벌스 전해 도금의 적용, 고 신뢰성 배선 형성을 위한 구리 기반 합금의 수퍼필링, 그리고 수퍼필링 특성 향상에 관한 다양한 연구를 소개한다. Cu interconnection in electronic devices is fabricated via damascene process including Cu electrodeposition. In this review, Cu electrodeposition and superfilling for fabricating Cu interconnection are introduced. Superfilling results from the influences of organic additives in the electrolyte for Cu electrodeposition, and this is enabled by the local enhancement of Cu electrodeposition at the bottom of filling feature formed on the wafer through manipulating the surface coverage of organic additives. The dimension of metal interconnection has been constantly reduced to increase the integrity of electronic devices, and the width of interconnection reaches the range of few tens of nanometer. This size reduction raises the issues, which are the deterioration of electrical property and the reliability of Cu interconnection, and the difficulty of Cu superfilling. The various researches on the development of organic additives for the modification of Cu microstructure, the application of pulse and pulse-reverse electrodeposition, Cu-based alloy superfilling for improvement of reliability, and the enhancement of superfilling phenomenon to overcome the current problems are addressed in this review.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2025264359","citationCount":21,"isOpenAccess":true,"pdfUrl":"http://koreascience.or.kr:80/article/JAKO201405262620564.pdf"},{"id":"oa-W2013701281","title":"Biomimetic nanolithography and its application for biosensor chip fabrication","authors":"Hiroshi Matsui","journal":"Proceedings of SPIE, the International Society for Optical Engineering/Proceedings of SPIE","pubDate":"2010-02-11","doi":"10.1117/12.846434","abstract":"Various nano-structures and complex patterns have been fabricated by top-down or bottom-up approaches, which have own strength and weakness. Here we combined the top-down and the bottom-up fabrications to take advantages on both strengths. We demonstrated that two different ways of the top-down/bottom-up combination could be very effective for the future nano-fabrications. One way is to assemble nanometer-sized building blocks into the device configurations such as electronics and sensor. Our strategy is to use those functionalized peptide nanowires, which can recognize and selectively bind a well-defined region on antigen-patterned substrates, as building blocks to assemble nanoscale architectures at uniquely defined positions, patterned by AFM-based nanolithography. The second method of the topdown/ bottom-up combination is to pattern mineralization peptides with nanolithography and grow metals along the peptide lines. For example, when an Au-mineralizing peptide was written in the line-array, the biomineralization yielded monodisperse Au-NPs along the peptide lines. We were also succeeded to grow and pattern semiconductors at room temperature as precursors were patterned with dip-pen nanolithography. This crystallization was induced by energy gain from the shape change caused by DPN. Then, hydrophobic-hydrophilic pattern that mimics protein-binding sites in nature could be patterned by DPN and this pattern geometry can induce the attachment-detachment switching of proteins. At last, the electronic pathogen sensor chips will be introduced as another example for the DPN application. Here the DPN was applied to attach single cell at a time on transducer surface, which unambiguously determined the single cell detection limit of the sensors.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2013701281","citationCount":2,"isOpenAccess":false,"pdfUrl":""},{"id":"oa-W122348984","title":"A Study of Nanometer Semiconductor Scaling Effects on Microelectronics Reliability","authors":"Mark White","journal":"University Libraries (University of Maryland)","pubDate":"2009-01-01","doi":"","abstract":"The desire to assess the reliability of emerging scaled microelectronics technologies through faster reliability trials and more accurate acceleration models is the precursor for further research and experimentation in this relevant field. The effect of semiconductor scaling on microelectronics product reliability is an important aspect to the high reliability application user. From the perspective of a customer or user, who in many cases must deal with very limited, if any, manufacturer's reliability data to assess the product for a highly-reliable application, product-level testing is critical in the characterization and reliability assessment of advanced nanometer semiconductor scaling effects on microelectronics reliability. This dissertation provides a methodology on how to accomplish this and provides techniques for deriving the expected product-level reliability on commercial memory products. Competing mechanism theory and the multiple failure mechanism model are applied to two separate experiments; scaled SRAM and SDRAM products. Accelerated stress testing at multiple conditions is applied at the product level of several scaled memory products to assess the performance degradation and product reliability. Acceleration models are derived for each case. For several scaled SDRAM products, retention time degradation is studied and two distinct soft error populations are observed with each technology generation: early breakdown, characterized by randomly distributed weak bits with Weibull slope Beta=1, and a main population breakdown with an increasing failure rate. Retention time soft error rates are calculated and a multiple failure mechanism acceleration model with parameters is derived for each technology. Defect densities are calculated and reflect a decreasing trend in the percentage of random defective bits for each successive product generation. A normalized soft error failure rate of the memory data retention time in FIT/Gb and FIT/cm2 for several scaled SDRAM generations is presented revealing a power relationship. General models describing the soft error rates across scaled product generations are presented. The analysis methodology may be applied to other scaled microelectronic products and key parameters.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W122348984","citationCount":2,"isOpenAccess":true,"pdfUrl":"http://hdl.handle.net/1903/9128"},{"id":"oa-W2937375035","title":"Rationale of the need to the development of semiconductor industry in Russia with the 28 nanometer semiconductor device fabrication node and below","authors":"Alena Vladimirovna Fomina, Viktoriia V. Frantsuzova, Ya I Petrenko, D V Kornachev, A R Avanesyan","journal":"IOP Conference Series Materials Science and Engineering","pubDate":"2019-04-16","doi":"10.1088/1757-899x/498/1/012043","abstract":"This article describes the systemic problem of the development of the Russian semiconductor industry due to the lack of national production of integrated microcircuits with topological standards below 65 nm. Here are the results of the analysis of the feasibility of production lines of integrated circuits developing, depending on the forecasted volume of demand for various categories of semiconductor products, the technological backlog of Russian organizations and the estimated cost of the project. In this article, there are suggestions on possible sources of project financing and measures of non-financial support. Also, it describes the general technological parameters of the created production. It contains an assessment of key performance indicators of the project and the impact of its implementation on related technological areas.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2937375035","citationCount":1,"isOpenAccess":true,"pdfUrl":"https://iopscience.iop.org/article/10.1088/1757-899X/498/1/012043/pdf"},{"id":"oa-W4414070220","title":"Integrating AI into Semiconductor Design and Fabrication: Methodologies, Challenges and Future Prospects","authors":"Nuo Chen","journal":"ITM Web of Conferences","pubDate":"2025-01-01","doi":"10.1051/itmconf/20257803007","abstract":"Semiconductor chips underpin modern electronics, yet conventional design and fabrication methods face escalating costs and diminishing returns as device geometries shrink. This review surveys the integration of artificial intelligence (AI) across chip development workflows, categorizing methodologies into supervised machine learning (e.g., SVM, decision trees), deep learning (CNN, RNN/LSTM/GRU, GAN), other AI paradigms (reinforcement, active, transfer learning; genetic algorithms; Bayesian optimization), and hybrid frameworks. In chip design, AI accelerates layout optimization, power‐performance trade‐off, and defect classification, while in fabrication it enhances wafer‐level defect detection, process monitoring, and production scheduling. Case studies illustrate GAN–CNN hybrids for noise‐robust fault diagnosis and GA–SVM/DT pipelines for failure prediction. Despite notable successes—such as sub‐nanometer feature prediction and real‐time anomaly detection—key challenges persist: scarcity of high‐quality, labeled datasets due to proprietary restrictions; the “black‐box” nature of deep models impeding interpretability; and a shortage of interdisciplinary expertise bridging AI and semiconductor domains. Future research should prioritize development of explainable models, federated or synthetic data generation strategies, and cross‐domain education to cultivate hybrid talent.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W4414070220","citationCount":1,"isOpenAccess":true,"pdfUrl":"https://www.itm-conferences.org/articles/itmconf/pdf/2025/09/itmconf_cseit2025_03007.pdf"},{"id":"oa-W2321204170","title":"Charting Progress In Semiconductor Fabrication","authors":"STEPHEN C. STINSON","journal":"Chemical & Engineering News","pubDate":"1999-09-13","doi":"10.1021/cen-v077n037.p037","abstract":"From the ACS meeting Electronic semiconductor devices are ubiquitous—from computers to cars to industrial process control. At a symposium on polymers for micropatterning and nanopatterning sponsored by the Division of Polymeric Materials: Science & Engineering, chemists reported progress in the fabrication of such devices. Their progress will make possible the data-processing units and memory chips of the future. A key semiconductor fabrication technology is microlithography—the etching, doping, and plating of devices onto semiconductor surfaces at resolutions of micrometers to nanometers. Achieving ever-finer patterns—needed for smaller and faster devices—depends on polymeric resins called photoresists. It became clear during the symposium that microlithography might eventually be superseded by advances in new technologies—\"drawing\" of patterns on resist layers by electron beams, for example, or \"printing,\" \"rubberstamping,\" or molding of images at exquisitely fine resolution onto semiconductor surfaces. But as several sessions made clear, advances are still being made in microlithography at the finer resolutions made possible by ...","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2321204170","citationCount":0,"isOpenAccess":false,"pdfUrl":""},{"id":"oa-W4401964319","title":"Revitalizing U.S. Semiconductor Manufacturing: The Strategic Impact of the CHIPS Act on Advanced Packaging and Fabrication Technologies","authors":"Shubham Rajendra Ekatpure","journal":"International Journal of Science and Research (IJSR)","pubDate":"2024-08-05","doi":"10.21275/sr24824030107","abstract":"The semiconductor industry is integral to modern electronics, yet the United States has seen a decline in its manufacturing capabilities due to offshoring. The CHIPS Act of 2022 aims to revitalize U.S. semiconductor manufacturing by providing substantial funding and incentives. This paper explores the U.S.s position in the global semiconductor market, analyzes the potential impact of the CHIPS Act, and evaluates investment strategies that could enhance domestic production. A high growth investment scenario, focusing on advanced packaging and leading-edge fabrication technologies, is proposed to meet rising technological demands, strengthen supply chain security, and maintain global competitiveness.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W4401964319","citationCount":0,"isOpenAccess":true,"pdfUrl":"http://dx.doi.org/10.21275/sr24824030107"},{"id":"oa-W2252330829","title":"Methods for self-fabrication chips","authors":"Jeremy A. Levitan","journal":"DSpace@MIT (Massachusetts Institute of Technology)","pubDate":"2000-01-01","doi":"","abstract":"Thesis (S.M.)--Massachusetts Institute of Technology, Dept. of Mechanical Engineering, February 2001.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W2252330829","citationCount":0,"isOpenAccess":true,"pdfUrl":"http://hdl.handle.net/1721.1/89313"},{"id":"oa-W4413737602","title":"A Comparative Review of RIE, ICP-RIE, and ALE: Dry Etching Technologies for Advanced Semiconductor Fabrication","authors":"Qiange Ren","journal":"Theoretical and Natural Science","pubDate":"2025-08-27","doi":"10.54254/2753-8818/2025.ad26235","abstract":"As the semiconductor industry continues to evolve rapidly to meet the growing demand for high-performance, low-power chips driven by technologies such as artificial intelligence (AI) and 5G, process nodes have progressed to sub-nanometer scales. This advancement introduces increased challenges in terms of structural complexity, material diversity, and precision requirements. In this context, etching plays a critical role in enabling accurate pattern transfer and the formation of nanoscale structures throughout device fabrication. This paper reviews the development of semiconductor etching technologies by systematically introducing the working principles, key advantages, application scenarios, and inherent limitations of three mainstream dry etching methods: Reactive Ion Etching (RIE), Inductively Coupled Plasma Reactive Ion Etching (ICP-RIE), and Atomic Layer Etching (ALE). Through comparative analysis, ALE demonstrates significant advantages due to its atomic-level precision and low-damage characteristics. The paper highlights ALE’s unique strengths and its potential as a next-generation mainstream etching technology, while also discussing current limitations and future research directions.","tldr":"","source":"OpenAlex","sourceUrl":"https://openalex.org/W4413737602","citationCount":0,"isOpenAccess":true,"pdfUrl":"https://www.ewadirect.com/proceedings/tns/article/view/26235/pdf"}],"links":{"web":"https://science-database.com/technology/semiconductor","llms_txt":"https://science-database.com/technology/semiconductor/llms.txt","api":"https://science-database.com/api/v1/technology/semiconductor"}}